Network on a chip based systems (NOCS) are systems wherein a plurality of processing modules are coupled to each other over a network interface. Some of the processing modules may be master processing modules (Master) who initiate transactions. Some of the processing modules may be slave processing modules (Slave) who receive the transactions from the Master and process the transactions. The NOCS may follow various architectures or standards so as to communicate and transact between the plurality of processing modules.
One such architecture is Advanced Micro controller Bus Architecture (AMBA). Advanced eXtensible Interface (AXI) is one of the bus standards supported by AMBA. AXI consists of five independent channels: Address Write (AW), Address Read (AR), Write data (W), Read data (R), and Write response (B). These multiple independent channels provide for better support for out-of-order transaction completion. These independent channels are utilized using a transaction ID, when a transaction is in progress.
In an AXI system, out of order transaction is achieved by using independent transaction ID. Number of different transaction IDs issued by a Master depends on the internal characteristic of the Master. For example, in a Direct Memory Access (DMA) Master, the number of transaction IDs may be limited to the number of DMA channels available in the DMA Master. In a processor based Master, the number of transaction IDs may be limited to the number of cache line fetches, instruction and data fetches etc. Due to these limited transaction IDs, requests that are issued to a Slave with the same transaction ID would be completed in order, by the Slave. This may in some systems lead to inefficient system bandwidth utilization. Inefficient system bandwidth may lead to inferior system performance.
Existing techniques for transaction ID allocation may not efficiently utilize available system bandwidth and may lead to poor system performance.